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description the A8503 is a multi-output wled/rgb led driver for medium-size lcd backlighting. it integrates a current-mode boost converter with internal power switch and six current sinks. the boost converter can provide output voltages up to 47 v. the boost converter can drive up to 72 leds at 20 ma per led with a battery voltage down to 5 v. the led sinks are capable of sinking up to 32 ma each, and can also be paralleled together to achieve even higher led currents. the A8503 provides protection against overvoltage, open diode, open or shorted led string, and overtemperature. a dual level cycle-by-cycle current limit function provides soft start and protects against overloads. a soft start timeout monitor is provided to enhance protection when starting up into a fault condition. when the mode pin is set low, the A8503 latches on a fault, and can be re-enabled only by cycling the input voltage, v in , or by toggling the en pin. connecting the mode pin high provides auto-restart after fault events. the A8503 features 8503-ds features and benefits ? active current sharing between led strings for 0.6% accuracy and matching ? drives up to 12 series 6 parallel = 72 leds (v f = 3.2 v, i f = 20 ma) at 5 v ? each individual current sink is capable of 32 ma ? adjustable overvoltage protection (ovp) ? 600 khz to 2 mhz adjustable switching frequency ? open or shorted led string protection ? open schottky diode protection ? overtemperature, cycle-by-cycle current limit, undervoltage, and soft start time-out protections ? selectable latched/auto-restart protection modes ? no audible mlcc noise during pwm dimming ? no pull-up resistors required for led modules that use esd capacitors high efficiency 6-channel, 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch package: 26 contact mlp/qfn (suffix ec) typical application A8503 approximate size applications ? notebook and sub-notebook displays ? lcd monitors ? lcd panels figure 1. typical application circuit mode pwm fset pad comp iset r iset led state on off off off off pwm en shutdown enable d1 l1 10 h r ovp r fset sw sw ovp v bat 5 to 22 v v in 4.3 to 5.5 v A8503 led4 led3 led2 led6 led5 led1 en c comp 1 f vin c in 0.1 f r pullup c out 2.2 f c bat 4.7 f 35 v fault fault dgnd lgnd agnd pgnd pgnd continued on the next page? continued on the next page?
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units sw pins v sw ?0.3 to 57 v led1 through led6 pins v ledx ?0.3 to 34 v ovp pin v ovp ?0.3 to 47 v remaining pins ?0.3 to 7 v operating ambient temperature t a range g ?40 to 105 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number packing package A8503gectr-t 1500 pieces per 7-in. reel 26-pin qfn/mlp with exposed thermal pad thermal characteristics characteristic symbol test conditions* value units package thermal resistance r ja on 4-layer pcb based on jedec standard 35 oc/w *additional thermal information available on the allegro website en (enable) and pwm (dimming) pins to comply with popular notebook backlight control interfaces. the device package is a 26-contact, 4 mm 4 mm, 0.75 mm nominal overall height qfn, with exposed pad for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin leadframe plating. description (continued) ? extends battery life ? efficiency optimized for 3-cell notebooks ? 0.1 a shutdown current ? unique architecture eliminates external voltage divider and associated battery drain ? rugged and small footprint solution ? 55 v, 2 a dmos switch in 4 mm 4 mm package?allows ipc-2221/2 / ipc-d-275 compliant pcb layout features and benefits (continued)
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com on/off + - led3 led6 led5 led4 agnd pgnd en osc sw ovp pgnd pgnd dgnd l 10 h 10 k vbat 5 to 22 v ovp comparators cbat 4.7 f/35 v cin 0.1 f reference current generator current mode boost controller c out v out 2.2 f led2 led1 sw led-select logic tsd ovp p iset wm vin 4.3 to 5.5 v vin r fset uvlo internal power latch reset flip-flop shut down r s + - ocp soft start ref open and short led detect ovp ocp fault fset fault rpullup comp c comp 1 f lgnd feedback and control mode r ovp functional block diagram
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram pad 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 26 25 24 23 22 nc ovp sw sw nc led1 led2 led3 lgnd led4 led5 led6 pgnd pgnd pwm dgnd en fault nc nc comp vin iset agnd fset mode (top view) terminal list table number name function 1, 15, 22, 26 nc not connected internally 2 comp compensation pin; connect 1 f capacitor to agnd or common star ground 3 vin input supply for the ic; decouple with a 0.1 f ceramic capacitor 4 iset sets 100% current through led string; connect r iset from iset to agnd 5 agnd connect to common star ground 6 fset set switching frequency; connect r fset from fset to agnd 7 mode apply v il for latching faults, apply v ih for auto-restart; see fault mode table 8, 9, 10, 12, 13, 14 ledx led current sinks; connect unused ledx pins to ground 11 lgnd power ground pin for ledx current sinks; connect to common star ground 16 f a u l t during normal operation, this pin is high (high impedance); at a fault event, this pin pulls low 17 en device enable 18 dgnd digital ground; connect to common star ground 19 pwm pwm led-current control; apply logic level pwm for dimming 20, 21 pgnd power ground; connect both pins to common star ground 23, 24 sw dmos switch drain node; tie both pins together on the pcb 25 ovp connect this pin to output capacitor +ve node through r ovp to enable overvoltage protection; select r ovp > 10 k (v ovp is 44 v typical) ? pad exposed thermal pad, common star ground for pgnd, dgnd, lgnd, and agnd; connect to copper plane of the application pcb for heat transfer
continued on the next page? high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 valid using circuit shown in figure 1, t a = t j = 25c except indicates specifications guaranteed from ? 40c to 105c, v in = 5.0 v, en = pwm = v ih , r iset = 12.4 k , r fset = 34 k , mode = agnd , unless otherwise noted characteristics symbol test conditions min. typ. 2 max. unit input voltage range v in 4.2 ? 5.5 v undervoltage lockout threshold v uvlo v in falling ? ? 4.0 v undervoltage lockout hysteresis window v uvlohys ? 0.1 ? v supply current i vin switching, at no load ? 7 ? ma shutdown, en= v il , t a = 25c ? 0.1 1 a standby, en = v ih , pwm = v il ? 1 2 ma boost controller switching frequency f sw 1.2 1.5 1.9 mhz minimum switch off-time t off(min) ? 72 ? ns minimum switch on-time t on(min) ? 72 ? ns logic input levels (en and pwm pins) input voltage level low v il ? ? 0.4 v input voltage level high v ih 1.5 ? ? v input leakage current i ilkg en = pwm = 5 v ? 100 ? a overvoltage protection output overvoltage threshold v ovp ?44? v overvoltage protection leakage current i ovplkg v ovp = 22 v, r ovp = 0 , en = v il ? 0.1 ? a overvoltage protection sense current i ovph ? 240 ? a boost switch switch on-resistance r ds(on) i sw = 1 a ? 250 ? m switch leakage current i swlkg(b) v sw = 22 v ? 0.1 ? a switch current limit i swlim ? 2.7 ? a led current sinks ledx pin regulation voltage v ledx ? 600 ? mv i set to i ledx current gain a iset i set = 100 a ? 320 ? a/a iset pin voltage v iset ? 1.235 ? v iset allowable current range i set 33 ? 100 a ledx current accuracy 3 err iledx led1 through led6 = 0.6 v, at 100% current ?3 0.6 3 % ledx current matching 4 ? i ledx i set = 100 a, led1 though led6 = 0.6 v, at 100% current ?3 0.6 3 % switch leakage current (ledx) i swlkg(l) v ledx = 12 v, en = 0 ? 0.1 ? a led short-detect voltage v sc ledx pin voltage level that forces latched shutdown, mode = low ? 18.7 ? v
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com soft start soft start boost current limit i sw(ss) initial soft start current for boost switch ? 0.4 ? a soft start ledx current limit i led(ss) current through enabled ledx pins during soft start ? 2.6 ? ma soft start timeout t to(ss) the longest duration the boost is allowed to operate during soft start ? 131,072 ? clock cycles thermal shutdown threshold t shdn t j rising ? 165 ? c thermal shutdown hysteresis t shdn(hys) ? 45 ? c f a u l t pin f a u l t pull-down voltage v fault voltage on f a u l t pin with fault enabled, 10 k pull-up resistor, to 3.3 v ? ? 0.4 v f a u l t pull-down resistance r fault resistance between f a u l t pin and ground with fault enabled, i fault = 100 a ?77? 1 specifications over the range t a = -40c to 105c; guaranteed by design and characterization. 2 typical values are at t a = 25c. 3 led accuracy is defined as 100 (i set 320 ? i led(av) ) / (i set 320), i led(av) measured as the average of i led1 through i led6 . 4 led current matching is defined as (i ledx ? i led(av) ) / i led(av) , with i led(av) as defined in footnote 3. electrical characteristics 1 (continued) valid using circuit shown in figure 1, t a = t j = 25c except indicates specifications guaranteed from ? 40c to 105c, v in = 5.0 v, en = pwm = v ih , r iset = 12.4 k , r fset = 34 k , mode = agnd , unless otherwise noted characteristics symbol test conditions min. typ. 2 max. unit
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 70 75 80 85 90 95 100 020406080100 v bat (v) 5 9 12 17 21 duty cycle (%) efficiency (%) 70 75 80 85 90 95 100 020406080100 v bat (v) 5 9 12 17 21 duty cycle (%) efficiency (%) characteristic performance high efficiency boost converter pwm efficiency at various input voltage levels (v bat ) v in = 5 v, six channels with 9 series leds each, 20 ma per channel, pwm = 200 hz, f sw = 1.5 mhz pwm efficiency at various input voltage levels (v bat ) v in = 5 v, six channels with 9 series leds each, 20 ma per channel, pwm = 200 hz, f sw = 980 khz
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 87 88 89 90 91 92 93 94 95 96 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v bat (v) 25 120 v out (v) i out (ma) 25 100 30 120 30 100 efficiency (%) 87 86 88 89 90 91 92 93 94 95 96 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v bat (v) 1.5 i sw (mhz) 1.0 2.0 efficiency (%) characteristic performance high efficiency boost converter efficiency (p out /p bat ) versus battery supply voltage for various output power levels l1 = 6.8 h, f sw = 1.5 mhz, v in = 5.0 v efficiency (p out /p bat ) versus battery supply voltage for various switching frequencies v in = 5.0 v, v out = 30 v i out = 120 ma
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com (b) turn-on using the vin pin, with en high symbol parameter units/division c1 v in 2 v c2 i out 20 ma t time 2 ms v in i out t c2 c1 (a) turn-on using the en pin, with v in = 5 v symbol parameter units/division c1 v en 2 v c2 i out 20 ma t time 2 ms v en i out t c2 c1 (c) shutdown using the en pin symbol parameter units/division c1 v en 2 v c2 i out 20 ma t time 200 s v en i out t c2 c1 characteristic performance turn-on and shutdown v in = 5 v, v bat = 7 v, i ledx = 20 ma, six led channels with 10 series leds each
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance average led current a various pwm duty cycles v in = 5.0 v, v bat = 12 v, pwm = 200 hz, output = six led channels with 10 series leds each 0.1 1 10 100 1 10 100 pwm duty cycle (%) i out (ma)
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description the A8503 is a multi-output wled/rgb led driver for backlighting medium-size displays. it has an integrated boost converter to increase input supply voltage, allowing it to drive up to 12 leds per channel on 6 channels with a v f (max) of 3.2 v at 20 ma per led, at 5 v supply. the boost converter is a fixed frequency current-mode converter. the switching frequency can be set in a range from 600 khz to 2 mhz, by an external resis- tor, r fset , connected between fset and ground. the integrated boost dmos switch is rated for 55 v, 2 a. this switch is pro- tected against overvoltage, and has pulse-by-pulse current limit- ing. the current limiting is independent of duty cycle. the A8503 has six well-matched current sinks that provide regulated current through the leds, for uniform display bright- ness. the boost converter is controlled by monitoring all ledx pins simultaneously and continuously. all led sinks are rated for 34 v to allow pwm dimming control. led current setting the maximum led current can be set, to 32 ma/channel, through the iset pin. connect a resistor, r iset , between this pin and ground to set the reference current level, i set . the value of i set (ma) is determined by: i set = 1.235 / r iset (k ) . the resulting current is multiplied internally by a gain of 320, then is mirrored to all enabled ledx pins. this sets the maximum current through ledx, referred as the 100% current , as shown in figure 2a. the ledx current can be reduced from the 100% current value by applying an external pwm signal on the pwm pin (see figure 2b). boost switching frequency setting connect an external resistor between the fset pin and agnd, to set boost switching frequency, f sw . the value of the boost switching frequency, f sw (mhz), is determined by: f sw = 52 / r fset (k ) . the typical r fset versus frequency curve is shown in figure 3. enable the ic turns on when a high signal is applied on the en pin and turns off when this pin is pulled low. pwm dimming the A8503 has a very wide range of pwm signal input. it can accept a pwm signal from 100 hz to 5 khz. when a pwm high signal is applied, the ledx pins sink 100% current. when the 4.5 5.0 5.5 v in (v) 0.6 0.8 1 1.2 1.4 1.6 1.8 2 25 30 35 40 45 50 55 60 65 70 75 80 85 r fset (k ) f sw (mhz) figure 3. switching frequency setting versus r fset (v in = 5 v, v bat = 12 v). 10 12 14 16 18 20 22 24 26 28 30 32 34 12 14 16 18 20 22 24 26 28 30 32 34 36 38 r iset (k ) i led (ma) 315 317 319 321 323 325 12 14 16 18 20 22 24 26 28 30 32 34 36 38 r iset (k ) gain 4.5 5.0 5.5 v in (v) figure 2. effect of value of r iset on current through an led string. panel a shows level of 100% current, and panel b shows ledx gain. (a) (b)
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pwm signal is low, the led sinks turn off. referring to figure 5, there is a 4 s ramp-up delay between when the pwm signal is applied and when the current reaches the 90% level. increase the applied pwm pulse-width by 3 s to compensate for this delay. startup sequence when en is pulled high, the ic enters soft start. the ic first tries to determine which ledx pins are being used, by raising the ledx pin voltage with a small current. after a duration of 512 switching cycles, the ledx pin voltage is checked. any ledx channel with a drain voltage smaller then 100 mv is removed from the control loop. after the first pwm positive trigger, the boost current is limited to 0.4 a and all active ledx pins sink 1 / 12 of the set current until output voltage reaches sufficient regulation level. when the device comes out of soft start, boost current and the ledx pin currents are set to normal operating level. within a few cycles, the output capacitor charges to the voltage required to supply full ledx current. after v out reaches the required level, ledx current toggles between 0% and 100% with each pwm command signal. in case of a heavy overload on output voltage at startup, the device may stay in soft start mode indefinitely, if the output volt- age cannot rise to the led regulation level and the mode pin is tied high. to avoid this scenario, A8503 has a soft start timeout when the mode pin is tied low. with the mode pin low, if the device does not finish soft start during 131,072 switching cycles, it is shut down. led open and short detect all unused led pins should be connected to ground to prevent any undesired faults from triggering. for led short detect, any enabled ledx pins that have a voltage exceeding the short circuit detect voltage, v sc , causes the device to shut down irrespective of what mode the A8503 is in. the open led fault will be triggered as soon as an enabled ledx pin does not have sufficient current flow- ing through it to stay in regulation. this will result in increased output voltage until the led is back in regulation or overvoltage protection (ovp) is tripped. if ovp is tripped, depending on the mode of operation, the A8503 will either shut down (mode = low) or will remove the led string from operation and continue to operate normally (mode = high). please refer to the fault mode table for latched and non-latched fault conditions. overvoltage protection the A8503 has two independent overvoltage protection features to protect the device against output overvoltage. the overvoltage level can be set, from 44 to 50 v typical, with an external resistor, rovp. when the current though the ovp pin exceeds 240 a, the ovp comparator goes high and the device shuts down in an ovp fault state when the mode pin is low. if the mode pin is high, the ovp fault disables all ledx strings that are below regu- lation, thus preventing them from controlling the boost output voltage. the device also offers open schottky diode protection. if for any reason the voltage on the sw pins exceeds more than 57 v, the ic shuts down and remains latched irrespective of the mode pin level. the overvoltage protection circuit is shown in figure 6. calculate the value for r ovp as follows: r ovp = ( v ovp ? 44) / 240 a , where v ovp is the desired typical ovp level in v, and r ovp is in . overcurrent protection the ic provides pulse-by-pulse current limiting at 2.7 a for the boost mosfet. if the overcurrent fault state persists, the boost control loop will force the compensating capacitor to rise in volt- age until it reaches the overcurrent fault level. this fault shuts down the ic and is latched when mode pin is low (mode = agnd). if mode pin is high, the overcurrent fault forces the device into soft start. figure 5. i ledx versus pwm input pwm 90% current 4 s i ledx figure 4. pwm pin dimming, f pwm = 200 hz, duty cycle = 10%. c1, i out 50 ma / div; ; c2, v fpwm (signal on pwm pin) 2 v / div; c3, v out 5 v / div, ac coupled. v out v fpwm i out
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 6. overvoltage protection circuitry + ? s sw w o ov vp p 1.23 v ovp disable 22 k A8503 1.23 v latch + ? input uvlo the device is shut down when input voltage, v in , falls below v uvlo . thermal shutdown protection (tsd) the device shuts down when junction temperature exceeds 165c. if the mode pin is low, the thermal shutdown will latch the device off until en is pulled low or uvlo is triggered. the A8503 will recover automatically when the mode pin is high and the junction temperature falls below 120c. fault mode the mode pin controls the latching of faults as shown in the fault mode table. latched faults are reset when en is pulsed low or v in falls below uvlo level. fault mode table protection mode = agnd mode = v in description overvoltage protection latched auto-restart fault occurs when ovp pin exceeds v ovp threshold. used to protect the output voltage from damaging the part. open diode protection latched latched fault occurs when sw node exceeds the safe operating voltage of the boost dmos switch. typical value is 57 v. pulse-by-pulse current limiting auto-restart auto-restart fault occurs when the current through the dmos switch exceeds i swlim , 2.7 a typical. the dmos switch is turned off on a cycle-by-cycle basis. overcurrent protection latched auto-restart fault occurs when the comp pin exceeds the overcurrent detect threshold. multiple pulse-by-pulse current limits will cause the comp pin voltage to rise. after a time period determined by the comp current and the compensation capacitor, the comp voltage will exceed the overcurrent detect threshold and force a fault. overtemperature protection latched auto-restart fault occurs when the die temperature exceeds the overtemperature threshold, 165c typical. shorted led protection latched latched fault occurs when the ledx pin voltage exceeds v sc , 18.7 v typical. v in uvlo no no fault occurs when v in drops below v uvlo , 4.0 v typical. this fault resets all latched faults. soft start timeout latched auto-restart fault occurs if the ic is unable to finish soft start within approximately 131,000 clock cycles (approximately 74 ms at 1.73 mhz) after en is set high.
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information a typical application circuit for dimming an lcd monitor backlight with 72 leds is shown in figure 1. figure 7 shows two dimming methods: digital pwm control (pwm signal on the pwm pin) and analog pwm control, with the analog signal, v a , applied to the iset pin through a resistor, r a . the current flowing through r a can be calculated as: i a = ( v a ? v set ) / r a . this current changes the reference current, i set , as follows: i set = v set / r set ? ( v a ? v set ) / r a . led current can be changed by changing v a . iset can be changed in the range from 33 to 100 a. application circuit for 1000:1 dimming level a wider dimming range can be achieved by changing the refer- ence current, i set , while using pwm dimming. for higher output, current levels turn on q1 (see figure 8). r iset and r isetp set the 100% current level. this current level can be set up to 32 ma, and then it can be dimmed by applying 100% to 0.33% duty cycle on the pwm pin. the reference current can be reduced by turn- ing off q1. led current can be dimmed to 10 ma by reducing reference current through the iset pin. this provides a 1000:1 combined dimming level range. figure 9 shows the accuracy, err ledx , that results using this circuit. figure 7. typical application circuit for analog dimming with external dc voltage source v a . this method of dimming can be combined with digital pwm dimming. mode pwm fset pad comp iset r iset r a v a d1 l1 10 h r ovp r fset sw sw ovp v bat 5 to 22 v v in 4.3 to 5.5 v A8503 led4 led3 led2 led6 led5 led1 en pwm en c comp 1 f vin c in 0.1 f r pullup c out 2.2 f c bat 4.7 f 35 v fault fault dgnd lgnd agnd pgnd pgnd riset q1 iset A8503 risetp figure 8. configuration for 1000:1 dimming. 100 95 90 85 80 75 0.1 1.0 10.0 100.0 dimming level (%) accuracy (%) figure 9. typical accuracy, normalized to the 100% current level, versus dimming level, with f pwm = 100 hz.
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 11. typical application circuit for led modules with esd capacitors with values up to 10 nf. figure 10. typical application circuit with led channels paralleled together to achieve higher led current (up to 64 ma per string). mode pwm fset pad comp iset r iset d1 l1 10 h r fset r ovp sw sw ovp v bat 5 to 22 v v in 4.3 to 5.5 v A8503 led4 led3 led2 led6 led5 led1 en pwm en c comp 1 f vin c in 0.1 f r pullup c out 2.2 f c bat 4.7 f 35 v fault fault dgnd lgnd agnd pgnd pgnd all esd capacitors across led arrays are 0.1 f mode pwm fset pad comp iset r iset d1 l1 10 h r fset r ovp sw sw ovp v bat 5 to 22 v v in 4.3 to 5.5 v A8503 led4 led3 led2 led6 led5 led1 en pwm en c comp 1 f vin c in 0.1 f r pullup c out 2.2 f c bat 4.7 f 35 v fault fault dgnd lgnd agnd pgnd pgnd
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com recommended components table component rating part number source c bat 4.7 f / 35 v, x5r ceramic capacitor gmk316f475zg-t taiyo yuden c comp 1 f / 10 v c in 0.1 f / 10 v c out 2.2 f / 50 v, x7r grm31cr71h225ka88l murata d1 schottky diode 60 v, 1.5 a 10mq060ntrpbf international rectifier r fset 34 k , 1% r iset 19.6 k , 1% (for 20 ma led current) r ovp 10 k r pullup 10 k l1 10 h, 1.3 a slf6028t-100m1r3-pf tdk alternate inductors 6.8 h, 1.3 a d53lc a915ay-6r8m toko 4.7 h, 1.6 a np04szb 4r7n taiyo yuden
high efficiency 6 -channel , 2 mhz , wled/rgb driver for medium displays, with integrated 55 v power switch A8503 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ec, 26-pin mlp/qfn 0.95 c seating plane c 0.08 27x 26 26 2 1 1 2 26 2 1 a d c a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220wgge) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d reference land pattern layout (reference ipc7351 qfn40p400x400x80-29m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 1.23 1.10 1.23 1.10 2.45 2.45 4.00 0.20 0.40 4.00 4.00 0.15 4.00 0.15 0.75 0.05 0.20 0.05 0.40 0.40 +0.15 ?0.10 b pcb layout reference view top view bottom view for the latest version of this document, visit our website: www.allegromicro.com copyright ?2009, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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